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Salvage of PR #11045 (original by v1k22). Changes on top of the original commit: - Rename 'architecture-visualization-svg-diagrams' -> 'concept-diagrams' to differentiate from the existing architecture-diagram skill. architecture-diagram stays as the dark-themed Cocoon-style option for software/infra; concept-diagrams covers physics, chemistry, math, engineering, physical objects, and educational visuals. - Trigger description scoped to actual use cases; removed the 'always use this skill' language and long phrase-capture list to stop colliding with architecture-diagram, excalidraw, generative-widgets, manim-video. - Default output is now a standalone self-contained HTML file (works offline, no server). The preview server is opt-in and no longer part of the default workflow. - When the server IS used: bind to 127.0.0.1 instead of 0.0.0.0 (was a LAN exposure hazard on shared networks) and let the OS pick a free ephemeral port instead of hard-coding 22223 (collision prone). - Shrink SKILL.md from 1540 to 353 lines by extracting reusable material into linked files: - templates/template.html (host page with full CSS design system) - references/physical-shape-cookbook.md - references/infrastructure-patterns.md - references/dashboard-patterns.md All 15 examples kept intact. - Add dhandhalyabhavik@gmail.com -> v1k22 to AUTHOR_MAP. Preserves v1k22's authorship on the underlying commit.
236 lines
9.4 KiB
Markdown
236 lines
9.4 KiB
Markdown
# Out-of-Order CPU Core Microarchitecture
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A structural diagram showing the internal pipeline stages of a modern superscalar out-of-order CPU core. Demonstrates multi-stage vertical flow with parallel paths, fan-out patterns for execution ports, and a separate memory hierarchy sidebar.
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## Key Patterns Used
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- **Multi-stage vertical flow**: Six pipeline stages (Front End → Rename → Schedule → Execute → Retire)
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- **Parallel decode paths**: Main decode and µop cache bypass (dashed line for cache hit)
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- **Container grouping**: Logical stages grouped in colored containers
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- **Fan-out pattern**: Single scheduler dispatching to 6 execution ports
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- **Sidebar layout**: Memory hierarchy placed in separate column on right
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- **Stage labels**: Left-aligned labels indicating pipeline phase
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- **Color-coded semantics**: Different colors for each functional unit category
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## Diagram Type
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This is a **hybrid structural/flow** diagram:
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- **Flow aspect**: Instructions move top-to-bottom through pipeline stages
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- **Structural aspect**: Components are grouped by function (rename unit, execution cluster)
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- **Sidebar**: Memory hierarchy is architecturally separate but connected via data paths
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## Pipeline Stage Breakdown
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### Front End (Purple)
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```xml
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<!-- Fetch Unit -->
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<g class="node c-purple">
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<rect x="40" y="70" width="140" height="56" rx="8" stroke-width="0.5"/>
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<text class="th" x="110" y="90" text-anchor="middle" dominant-baseline="central">Fetch unit</text>
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<text class="ts" x="110" y="110" text-anchor="middle" dominant-baseline="central">6-wide, 32B/cycle</text>
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</g>
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<!-- Branch Predictor (subordinate) -->
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<g class="node c-purple">
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<rect x="40" y="140" width="140" height="44" rx="8" stroke-width="0.5"/>
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<text class="th" x="110" y="162" text-anchor="middle" dominant-baseline="central">Branch predictor</text>
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</g>
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<!-- Decode -->
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<g class="node c-purple">
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<rect x="230" y="70" width="160" height="56" rx="8" stroke-width="0.5"/>
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<text class="th" x="310" y="90" text-anchor="middle" dominant-baseline="central">Decode</text>
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<text class="ts" x="310" y="110" text-anchor="middle" dominant-baseline="central">x86 → µops, 6-wide</text>
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</g>
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```
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### µop Cache Bypass Path (Teal)
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The µop cache (Decoded Stream Buffer) provides an alternate path that bypasses the complex decoder:
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```xml
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<!-- µop Cache parallel to decode -->
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<g class="node c-teal">
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<rect x="230" y="150" width="160" height="50" rx="8" stroke-width="0.5"/>
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<text class="th" x="310" y="168" text-anchor="middle" dominant-baseline="central">µop cache (DSB)</text>
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<text class="ts" x="310" y="186" text-anchor="middle" dominant-baseline="central">4K entries, 8-wide</text>
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</g>
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<!-- Dashed bypass path indicating cache hit -->
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<path d="M180 110 L205 110 L205 175 L230 175" fill="none" class="arr"
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stroke-dasharray="4 3" marker-end="url(#arrow)"/>
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<text class="tx" x="164" y="148" opacity=".6">hit</text>
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```
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### Rename/Allocate Container (Coral)
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Groups related rename components in a container:
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```xml
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<!-- Outer container -->
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<g class="c-coral">
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<rect x="40" y="250" width="530" height="130" rx="12" stroke-width="0.5"/>
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<text class="th" x="60" y="274">Rename / allocate</text>
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<text class="ts" x="60" y="292">Map architectural → physical registers</text>
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</g>
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<!-- Inner components -->
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<g class="node c-coral">
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<rect x="60" y="310" width="180" height="56" rx="8" stroke-width="0.5"/>
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<text class="th" x="150" y="330" text-anchor="middle" dominant-baseline="central">Register alias table</text>
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<text class="ts" x="150" y="350" text-anchor="middle" dominant-baseline="central">180 physical regs</text>
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</g>
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```
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### Scheduler Fan-Out Pattern (Amber → Teal)
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Single unified scheduler dispatching to multiple execution ports:
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```xml
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<!-- Unified Scheduler -->
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<g class="node c-amber">
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<rect x="140" y="420" width="330" height="50" rx="8" stroke-width="0.5"/>
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<text class="th" x="305" y="438" text-anchor="middle" dominant-baseline="central">Unified scheduler</text>
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<text class="ts" x="305" y="456" text-anchor="middle" dominant-baseline="central">97 entries, out-of-order dispatch</text>
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</g>
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<!-- Fan-out arrows to 6 ports -->
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<line x1="170" y1="470" x2="90" y2="540" class="arr" marker-end="url(#arrow)"/>
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<line x1="215" y1="470" x2="170" y2="540" class="arr" marker-end="url(#arrow)"/>
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<line x1="265" y1="470" x2="250" y2="540" class="arr" marker-end="url(#arrow)"/>
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<line x1="305" y1="470" x2="330" y2="540" class="arr" marker-end="url(#arrow)"/>
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<line x1="355" y1="470" x2="410" y2="540" class="arr" marker-end="url(#arrow)"/>
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<line x1="420" y1="470" x2="490" y2="540" class="arr" marker-end="url(#arrow)"/>
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```
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### Execution Port Box Pattern
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Compact boxes showing port number and capabilities:
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```xml
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<!-- Execution port with multi-line capability -->
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<g class="node c-teal">
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<rect x="55" y="540" width="70" height="64" rx="6" stroke-width="0.5"/>
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<text class="th" x="90" y="560" text-anchor="middle" dominant-baseline="central">Port 0</text>
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<text class="tx" x="90" y="576" text-anchor="middle" dominant-baseline="central">ALU</text>
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<text class="tx" x="90" y="590" text-anchor="middle" dominant-baseline="central">DIV</text>
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</g>
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```
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### Reorder Buffer (Pink)
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Wide horizontal bar at bottom showing retirement:
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```xml
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<g class="c-pink">
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<rect x="40" y="670" width="530" height="40" rx="10" stroke-width="0.5"/>
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<text class="th" x="305" y="694" text-anchor="middle" dominant-baseline="central">Reorder buffer (ROB) — 512 entries, 8-wide retire</text>
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</g>
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```
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### Memory Hierarchy Sidebar (Blue)
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Separate column showing cache levels:
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```xml
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<!-- Container -->
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<g class="c-blue">
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<rect x="600" y="30" width="190" height="360" rx="16" stroke-width="0.5"/>
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<text class="th" x="695" y="54" text-anchor="middle">Memory hierarchy</text>
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</g>
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<!-- Cache levels stacked vertically -->
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<g class="node c-blue">
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<rect x="620" y="70" width="150" height="50" rx="8" stroke-width="0.5"/>
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<text class="th" x="695" y="88" text-anchor="middle" dominant-baseline="central">L1-I cache</text>
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<text class="ts" x="695" y="106" text-anchor="middle" dominant-baseline="central">32 KB, 8-way</text>
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</g>
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<!-- Additional levels follow same pattern -->
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```
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## Connection Patterns
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### Instruction Fetch Path
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Horizontal arrow from L1-I cache to fetch unit:
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```xml
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<path d="M620 95 L200 95" fill="none" class="arr" marker-end="url(#arrow)"/>
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<text class="tx" x="410" y="88" text-anchor="middle" opacity=".6">instruction fetch</text>
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```
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### Load/Store Path
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Complex path from execution ports to L1-D cache:
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```xml
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<path d="M250 604 L250 640 L580 640 L580 160 L620 160" fill="none" class="arr" marker-end="url(#arrow)"/>
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<text class="tx" x="415" y="652" text-anchor="middle" opacity=".6">load / store</text>
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```
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### Commit Path (dashed)
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Dashed line showing write-back from ROB to register file:
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```xml
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<path d="M550 690 L580 690 L580 445 L595 445" fill="none" class="arr" stroke-dasharray="4 3"/>
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<text class="tx" x="590" y="578" opacity=".6" transform="rotate(-90 590 578)">commit</text>
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```
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### Path Merge (Decode + µop Cache)
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Two paths converging before rename:
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```xml
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<line x1="390" y1="98" x2="430" y2="98" class="arr"/>
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<line x1="390" y1="175" x2="430" y2="175" class="arr"/>
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<path d="M430 98 L430 175" fill="none" stroke="var(--text-secondary)" stroke-width="1.5"/>
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<line x1="430" y1="136" x2="470" y2="136" class="arr" marker-end="url(#arrow)"/>
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```
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## Text Classes
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This diagram uses an additional text class for very small labels:
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```css
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.tx { font-family: system-ui, -apple-system, sans-serif; font-size: 10px; fill: var(--text-secondary); }
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```
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Used for:
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- Execution port capability labels (ALU, Branch, Load, etc.)
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- Connection labels (instruction fetch, load/store, commit)
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- DRAM latency annotation
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## Color Semantic Mapping
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| Color | Stage | Components |
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|-------|-------|------------|
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| `c-purple` | Front end | Fetch, Branch predictor, Decode |
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| `c-teal` | Execution | µop cache, Execution ports |
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| `c-coral` | Rename | RAT, Physical RF, Free list |
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| `c-amber` | Schedule | Unified scheduler |
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| `c-pink` | Retire | Reorder buffer |
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| `c-blue` | Memory | L1-I, L1-D, L2, DRAM |
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| `c-gray` | External | Off-chip DRAM |
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## Layout Notes
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- **ViewBox**: 820×720 (taller than wide for vertical pipeline flow)
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- **Main pipeline**: x=40 to x=570 (530px width)
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- **Memory sidebar**: x=600 to x=790 (190px width)
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- **Stage labels**: x=30, left-aligned, 50% opacity
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- **Vertical spacing**: ~80-100px between major stages
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- **Container padding**: 20px inside containers
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- **Port spacing**: 80px between execution port centers
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- **Legend**: Bottom-right of memory sidebar, explains color coding
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## Architectural Details Shown
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| Component | Specification | Notes |
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|-----------|---------------|-------|
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| Fetch | 6-wide, 32B/cycle | Typical modern Intel/AMD |
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| Decode | 6-wide, x86→µops | Complex decoder |
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| µop Cache | 4K entries, 8-wide | Bypass for hot code |
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| RAT | 180 physical regs | Supports deep OoO |
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| Scheduler | 97 entries | Unified RS |
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| Execution | 6 ports | ALU×2, Load, Store×2, Vector |
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| ROB | 512 entries, 8-wide | In-order retirement |
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| L1-I | 32 KB, 8-way | Instruction cache |
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| L1-D | 48 KB, 12-way | Data cache |
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| L2 | 1.25 MB, 20-way | Unified |
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| DRAM | DDR5-6400, ~80ns | Off-chip |
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## When to Use This Pattern
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Use this diagram style for:
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- CPU/GPU microarchitecture visualization
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- Compiler pipeline stages
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- Network packet processing pipelines
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- Any system with parallel execution units fed by a scheduler
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- Hardware designs with multiple functional units
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